FIGS. 1A to 1D illustrate a method of manufacturing a CMOS image sensor. In a method of manufacturing a CMOS image sensor, after a field insulating layer for electric insulation between elements is formed on a silicon substrate and light receiving elements such as a photo diode are formed, an interlayer insulating layer and a pad may be formed.
Passivation layers may be formed in order to protect elements or a pad. As illustrated in FIG. 1A, after applying an undoped silicate glass (USG) layer 100 and a d-tera ethyl ortho silicate (TEOS) layer 110 as passivation layers, a planarization process may be performed. A silicon nitride (SiN) passivation layer 120 may be applied to form passivation layers. USG passivation layer 100 may be applied at a thickness of approximately 10,000 Å and/or SiN passivation layer 120 may be applied at a thickness of approximately 3,000 Å.
As illustrated in FIG. 1B, color filters 130 may be formed by a color photolithography process. As illustrated in FIG. 1C, planarization layer 140 may be formed over color filters 130. As illustrated in FIG. 1D, a thermal reflow may be performed to form convex micro-lenses 150.
A pad passivation layer may be formed to have a thickness of about 15,000 Å. If a pad passivation layer has a thickness of about 15,000 Å (or another thickness that is relatively thick), the sensitivity of light that incident through micro-lenses 150 may be degraded. If color filters 130 and micro-lenses 150 are formed in separate processes, the processes may be complicated.